1. Field of the Invention
This invention relates to the semiconductor memory device which has the suitable structure for integration. Moreover, this invention relates to the manufacture method of a semiconductor memory device having the suitable structure for integration.
2. Description of the Related Art
An electrically erasable and programmable EEPROM, such as a NAND cell-type EEPROM that configures a NAND cell with a plurality of serially connected memory cells, has been known as one of semiconductor memory devices. A memory cell in the NAND cell-type EEPROM has a FETMOS structure with a charge storage layer (floating gate) and a control gate stacked on a semiconductor substrate. The memory cell stores data “0” or “1” depending on the amount of charge accumulated in the floating gate.
For market expansion of a semiconductor memory device, high integration of a semiconductor memory device and the reduction in cost are required. Therefore, it is necessary to make the pattern formed by optical lithography more detailed.
Reduced-projection-exposure equipment is used for the pattern formation of semiconductor equipment.
In order to make a pattern detailed, the large numerical aperture (NA) lens and the light source of short wavelength is used.
Furthermore, half-tone phase shift reticle is used increasingly.
The memory cell array of a semiconductor memory device has the pattern arranged periodically. Ultra-fine processing technology which was mentioned above is very effective technology to such a pattern. However, periodicity is deficient in the pattern of the end of a memory cell array.
Ultra-fine processing technology which was mentioned above is not much effective technology to the scarce pattern of periodicity.
In the case of a periodic scarce pattern, diffraction of light and the state of interference of light are differs from in the case of a periodic pattern.
Therefore, when exposure conditions are made suitable to the inside of a memory cell array, the exposure condition is not suitable for the pattern of the exterior of a memory cell array.
Therefore, the method which uses the memory cell structure located in the exterior of a memory cell array as the dummy memory cell which is not used electrically is disclosed in U.S. Patent No. 6531357.
The dummy memory cell which is not used electrically is not connected to the row decoder or the column decoder in the embodiment shown in this U.S. patent. However, common connection is made to the word line and bit line of a memory cell array. For this reason, when dummy memory cell receives a mechanical damage, the leak current of a memory cell array may increase.
The perimeter end of a dummy memory cell array is arranged inside from the perimeter end of a semiconductor chip by the above-mentioned reason.
Thereby, in case a chip is divided, mechanical damage does not reach the perimeter end of a dummy memory cell array from the perimeter end of a semiconductor chip. However, chip size increases.
This invention offers the semiconductor memory device having increased effective area in a chip, and its manufacture method, without increasing chip size.